Non-volatile memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. Examples of non-volatile memory devices include conventional electronically erasable programmable read-only memories (EEPROMs) and flash memories. A conventional EEPROM typically includes a plurality of dual-gate NAND memory gates arranged in an array on a semiconductor chip.
In a conventional NAND non-volatile memory array, the NAND memory gates are arranged in a plurality of rows and columns, with each row of the NAND gates connected to a respective word line and each column of the NAND gates connected to a respective bit line. Each NAND gate typically has a dual-gate structure which includes a floating gate, a control gate, and an interpolysilicon dielectric layer between the floating gate and the control gate. When the NAND flash memory circuit is implemented on a silicon-based semiconductor chip, the floating gates are formed by a patterned first polysilicon (POLY-1) layer, and the control gates are formed by a patterned second polysilicon (POLY-2) layer on top of the interpolysilicon layer and the POLY-1 layer. The bit lines are implemented on the semiconductor chip as metal layer strips which are connected across the respective columns of the NAND memory gates, whereas the word lines are implemented as POLY-2 layer strips which are connected across the control gates of the respective rows of the NAND memory gates.
In a conventional NAND flash memory array, the NAND gates on each word line are capable of storing a binary word consisting of a plurality of bits. The conventional NAND flash memory device has five modes of operation, including a program mode, a program verify mode, a read mode, an erase mode, and an erase verify mode. A page is defined as one word of memory storage on a single word line. A sector is defined as a plurality of pages, for example, sixteen pages of memory storage. During the operation of a conventional NAND flash memory array in the erase mode, a whole sector of memory cells is erased at a time. When the conventional NAND flash memory array is in the erase verify mode after the erase operation, the whole sector of memory cells is erase verified at a time.
A disadvantage of having to erase a whole sector of multiple pages of memory cells at a time is that an application may require the erasure of some of the words while retaining others in the same sector of memory cells. Because of the inconvenience of having to erase a whole sector of memory cells at a time, if some of the words in a sector are desired to be retained, the conventional NAND flash memory device would require rewriting the words which are to be retained after the erasure of the whole sector of memory cells. Therefore, there is a need for a NAND flash memory device and a method of erasing portions of a sector of memory cells without having to erase the whole sector.